The Enabling Interconnect Technology for Cost Effective 2.nD Package
Packaging technology has been evolving very fast and diversified since last decade. From application point of view, CSPs (Chip Scale Packages) and WLPs (Wafer Level Packages) has played dominating role in the low-end/mobile segment owing to their smaller form factor. For high-end application, 3D-IC has demonstrated its superior performance, yet it is still a long way for industry to adopt this technology widely not only because of its very high cost but also mainly due to technical challenges. 2.5D-IC is then invented as an alternative solution to dodge the difficulty of 3D-IC. However, 2.5D-IC is still too high cost to be adopted for most of the high-end to mid-range application. Thus, lots of alternative technologies were proposed to further reduce the cost while trying to maintain the similar level of performance. All the emerging technologies between conventional 2D architecture and 3D-IC are defined conceptually as 2.nD in terms of cost, performance, and integration density. Conventional chip-to-package interconnect technologies, i.e. wire-bonding (WB), tape-automatic-bonding (TAB), and big-pitch flip-chip-bonding (FCB) is no longer used for the new packages. Instead, via-interconnect, through-x-via, and micro-bump FCB are the dominating technologies to interconnect chip to package for those emerging packages.