EUV Computational Lithography to Enable Technology Scaling below 10 nm
Multiple patterning (MPT) has been the work horse for the semiconductor industry to drive device scaling down to 10 nm node using immersion lithography. EUV is on track for adoption at the 7 nm node, with development and production in the 2016-2017 time frames. ASML has been collaborating with the chip makers in a holistic lithography framework to tackle the multiple patterning lithography challenges with innovative hardware and software solutions, including scanner systems, computational lithography, metrology, and process control. For sub-10 nm nodes, multiple patterning runs into a major cost hurdle with exponentially increasing manufacturing complexity. EUV lithography is critical for the industry to continue the technology scaling.
EUV offers the much needed resolution and imaging capabilities to greatly simplify the patterning processes and reduce the manufacturing cost. It also presents some unique challenges compared to immersion lithography. This paper will discuss the EUV specific effects such as oblique incidence, 3D mask topography and stochastic effects that have to be considered in computational lithography for resolution enhancement and mask OPC to ensure accurate imaging with maximum process window. Examples are given to illustrate how these effects are handled in modeling and applications such that their impacts are well captured when optimizing scanner optics and mask OPC. Asymmetric SRAF placement is unique for EUV OPC to reduce pattern shift through focus while enlarging the process window. Different from immersion, EUV OPC needs to be processed on the full field level due to field and slit dependency of flare and 3D mask shadowing. Progress has been made to streamline full field OPC and bring the run time and file size under control for production tape-out. In summary, the EUV computational lithography solutions are ready for volume production at 7 nm node and below.