Topic:
Extending etch and deposition capabilities for implementation of 3D packaging of MEMS in volume production
Abstract:
MEMS and CMOS image sensors used in modern smartphones are increasingly packaged by WLCSP methods to minimise package size.  Through-silicon vias (TSVs) are created from the back of the wafer to contact the sensor on the frontside.  Referred to as “via-last”, because the TSV’s are formed after device fabrication,  tapered vias are often used to simplify integration with subsequent dielectric and metal lining steps.  With a relatively low I/O count and strong trend for miniaturization, MEMs is an ideal application to lead the evolution of 3D packaging solutions into volume production. This presentation will present and discuss the various silicon processes that have been developed to create a wide range of TSV profiles, both tapered (allowing relatively simple deposition processes) and vertical (reducing real estate). The presentation will cover process steps such as TSV etch, dielectric liner deposition, and barrier/seed PVD, which have been developed and optimized to increase electrical performance, increase throughput and reduce costs for volume production. We will also present how non-switched plasma etching can be used to create a variety of via profiles, and show how the same hardware can also be used to etch vertical TSVs using the “switched” Bosch Process, a technology which is already well-established in the MEMS industry.  This presentation will also describe unique end-pointing techniques that have been proven in production for both tapered and vertical vias.