The introduction of wafer level packaging strategies such as CSP and FO-CSP have the potential to radically reduce the size and power consumption of high volume mobile electronics. These devices also do not fit easily into the existing paradigm of "Wafer Test" and "Package Test". This talk will present an economic model to balance the quality, yield, cost of test and development cost impact of differing test strategies. The model will be used to discuss the strengths and weaknesses of test approaches including wafer level stress test, pre-singulation test and singulated device test.
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