Topic:
Computational Lithography Technology for Foundry
Abstract:
Facing the increasing complexity and decreasing k1 in critical lithography technology for the semiconductor manufacturing, traditional parametric simulation is no longer sufficient to fulfill the requirement for the process optimization. With the mighty computing power and the decreasing cost of modern chips, computer-aided design (CAD) tools are capable of optimizing the complex lithography variables to deliver practical solutions in terms of technology and cost globally. Computational lithography starts to play an important role accordingly for advanced generations, especially in extending the life of 193-nm immersion patterning with the latest optical and computational explorations. TSMC has adopted computational lithography technology for a wide spectrum of applications in optical proximity correction (OPC), resolution enhancement technology (RET), layout patterning check (LPC), design for manufacturing (DFM), design-technology co-optimization (DTCO), and manufacturability enhancement. Without extreme-UV (EUV) and e-beam lithography (EBL), model-based sub-resolution assist feature (MB-SRAF), inverse lithography technology (ILT), source mask optimization (SMO), double-dipole lithography (DDL), and double-patterning technology (DPT) are popular and decisive to enable the optical extension of the 193-nm immersion tool with computational lithography. It has been a must for the patterning processes to achieve the chip shrinkage following Moore’s law with innovative solutions to the engineering challenges of the day.