Topic:
Patterning Technology Inflections for the 10nm, 7nm and 5nm Logic Nodes
Abstract:
Dimensional scaling has driven logic and memory device roadmaps for the semiconductor industry over the last 5 decades. Continuous and disruptive innovation in optical lithography has been a key enabler of scaling, application of these innovations has allowed optical lithography to routinely operate near the theoretical limits of resolution in high volume production. Yet the relentless pace of device innovation requires patterning below the threshold of what is possible using direct printed immersion lithography. Innovations in patterning, such as multiple spacer patterning and multi-color pitch splitting, have been introduced into high volume manufacturing to enable scaling to continue while the industry simultaneously develops next generation lithography. The opportunities and challenges associated with these patterning technology inflections for scaling will be reviewed. Extension of available imaging resolution requires a new paradigm of patterning integration, leveraging the resolution enhancement capabilities of downstream processes. Specific technical challenges and opportunities of patterning integration such as complex patterning trim and shrink processes, line edge roughness mitigation, and self-aligned patterning techniques will be examined. New opportunities for collaborative innovation across lithography, materials, etch, deposition, and clean are required to meet these challenges. The role of these collaborative partnerships between research consortia, equipment suppliers, and leading edge technology manufacturers will become increasingly critical to accelerate these patterning innovations toward readiness for high volume manufacturing.