This can be viewed as a merge between the Embedded Die technology based on PWB infrastructure and the FOWLP on Wafer Level. The first being low cost by nature due to PWB technology but the supply chain is still complex because the PWB industry is not used to work with bare dies. Also the routing density is not fitting the WLP demands. Tight pad pitches require a redistribution of the dies before embedding ending up with higher cost for the total package. Therefore the first products have been power modules due to the possibilities of plating thick copper and the low number of I/Os of the IGBTs and MOSFETs. An additional advantage of the embedding die concept is the existing TPV (through package via) possibility which enables 3D packaging. In contrast to embedding die the FOWLP approach can use existing WLP equipment mostly installed at OSATs and some of the IDMs. Due to the higher resolution of the wafer lithography tighter pad pitches can be redistributed. Digital chip IC applications with a pin count of 100 to 250 are on the short term. Current limitation of the package size have to be extended for fully SiP including passive elements especially antennas.
Thin film processing has been also developed to large panel format for photovoltaic modules and displays. Therefore lithography with resolution down to 2 µm is available for large format. On the other side dimensions on the PWB are constantly decreasing. Embedding chips has opened the possibility to SiP. FO-WLP on panel size is now seen as the optimal synergy for SiP with high performance keeping the cost at a reasonable low level. However, for a reliable and high yield production developments and optimizations have to be done in the fields of materials, equipment and processes.
In summary this presentation will give a status and an outlook on Fan-out Panel Level Packaging.