• Srini Raghvendra first joined Synopsys as an R&D Engineer in 1989 when Synopsys was a small startup company. Since then he has worked in roles of increasing responsibility in areas of logic synthesis, low power synthesis, physical synthesis, and mask synthesis. He has held roles of R&D engineer, R&D manager and R&D director, and now vice president.
• He contributed to the development of the industry’s first commercial Verilog and VHDL compilers for synthesis, and is a co-author on 2 early patents in this area. He has wide-ranging experience in R&D, marketing, strategy and M&A, and product engineering, and has received several achievement awards at Synopsys. He has delivered several invited talks and participated in many industry panels and program committees.
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